NXP Semiconductors /LPC15xx /I2C0 /INTENCLR

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Interpret as INTENCLR

Description

Interrupt Enable Clear register.

Fields

MSTPENDINGCLR	Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented.
RESERVED	Reserved. Read value is undefined, only zero should be written.
MSTARBLOSSCLR	Master Arbitration Loss interrupt clear.
RESERVED	Reserved. Read value is undefined, only zero should be written.
MSTSTSTPERRCLR	Master Start/Stop Error interrupt clear.
RESERVED	Reserved. Read value is undefined, only zero should be written.
SLVPENDINGCLR	Slave Pending interrupt clear.
RESERVED	Reserved. Read value is undefined, only zero should be written.
SLVNOTSTRCLR	Slave Not Stretching interrupt clear.
RESERVED	Reserved. Read value is undefined, only zero should be written.
SLVDESELCLR	Slave Deselect interrupt clear.
MONRDYCLR	Monitor data Ready interrupt clear.
MONOVCLR	Monitor Overrun interrupt clear.
RESERVED	Reserved. Read value is undefined, only zero should be written.
MONIDLECLR	Monitor Idle interrupt clear.
RESERVED	Reserved. Read value is undefined, only zero should be written.
EVENTTIMEOUTCLR	Event time-out interrupt clear.
SCLTIMEOUTCLR	SCL time-out interrupt clear.
RESERVED	Reserved. Read value is undefined, only zero should be written.

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